SmartDV’s JTAG Master IP is a silicon-proven, fully featured boundary scan controller engineered for SoC designs requiring reliable, standards-compliant test access and debug control. Compliant with IEEE 1149.1-2013 and IEEE 1149.6, it provides complete TAP controller functionality with support for all standard JTAG instructions, making it a versatile solution for device testing, board-level debug, and in-system programming across a wide range of ASIC and FPGA applications.
Beyond basic boundary scan, the IP’s support for IEEE 1149.6 extends its test coverage into AC-coupled and differential signal domains — areas where standard IEEE 1149.1 falls short in modern high-speed SoC designs. Combined with programmable clock frequency and configurable instruction and data register sizes, it gives design and test teams a flexible, integration-ready JTAG master that adapts to the specific requirements of each target device.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and straightforward host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
