SmartDV’s JTAG Slave IP is a silicon-proven, fully featured boundary scan solution engineered for SoC designs requiring reliable, standards-compliant test access and debug capability from an external JTAG master. Compliant with IEEE 1149.1-2013 and IEEE 1149.6, it provides complete TAP controller functionality with support for all standard JTAG instructions, making it a versatile solution for device testing, board-level debug, and in-system programming across a wide range of ASIC and FPGA applications.
Its support for IEEE 1149.6 extends test coverage into AC-coupled and differential signal domains, addressing the limitations of standard IEEE 1149.1 in modern high-speed SoC designs. Combined with programmable clock frequency and configurable instruction and data register sizes, it gives design and test teams a flexible, integration-ready JTAG slave that adapts to the specific test requirements of each target device and host test environment.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and straightforward host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
