SmartDV’s JTAG Synthesizable Transactor is a fully featured JTAG boundary scan bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable JTAG TAP controller behavior during pre-silicon validation and software bring-up. Fully compliant with IEEE 1149.1-2013 and IEEE 1149.6, it delivers complete JTAG master and slave functionality with all standard TAP instructions, programmable clock frequency, and BSDL file-driven automatic test vector and coverage generation, giving validation teams a drop-in synthesizable JTAG transactor ready for rapid integration into emulation and prototyping flows.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports state-based rule checking, active command rule checking, instruction and data register read/write rule checking, user-defined instruction and register extensions, user-defined functional coverage points, and automatic SVA assertion property generation from BSDL files, enabling validation teams to exercise corner-case JTAG behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its BSDL-driven automatic test vector generation covering all cell types, automatic functional coverage point generation, and complete testsuite covering every feature of the JTAG specification enable rapid deployment for early software bring-up and comprehensive boundary scan validation regardless of the underlying emulation platform.
