SmartDV’s IEEE 1149.7 DTS Adapter IP is a silicon-proven, fully featured Debug Test System Adapter solution purpose-built for SoC designs requiring standards-compliant reduced-pin cJTAG debug host-side connectivity across System-on-Chip, System-on-Package, and Package-on-Package applications. Fully compliant with IEEE 1149.7-2009 (cJTAG), it delivers complete DTS Adapter functionality supporting all six IEEE 1149.7 classes T0 through T5, generating reset and escape sequences for TAP controller management on the host debug tool side of a cJTAG link.
Designed to serve as the debug tool-side complement to a Compact TAP target, the IP implements the Extended Protocol Unit (EPU) for Classes T0 through T3 with all mandatory and optional commands, and the Advanced Protocol Unit (APU) for Classes T4 and T5. Its Transport function supporting 1 or 2 physical data channels with up to 16 data channel clients each, support for both 4-pin and 2-pin interface configurations, and all mandatory and optional scan formats (JScan, MScan, OScan, and SScan) give debug tool and probe SoC teams a production-tested, spec-complete DTS Adapter implementation.
Built for design flexibility and silicon efficiency, the IP core is fully synthesizable, and is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized class and topology architecture and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
