SmartDV’s IEEE 1149.7 Compact TAP IP is a silicon-proven, fully featured reduced-pin Test Access Port solution purpose-built for SoC designs requiring standards-compliant boundary scan and debug connectivity across System-on-Chip, System-on-Package, and Package-on-Package applications. Fully compliant with IEEE 1149.7-2009 (cJTAG), it delivers complete TAP.7 capability supporting all six classes T0 through T5, extending the traditional IEEE 1149.1 four-wire TAP with reduced two-pin operation while maintaining full backward compatibility.
Designed to address the pin count, multi-die, and power-sensitive test requirements of modern SoC and stacked-die packaging, the IP implements the Reset and Selection Unit (RSU) for Class T0 optional features, the Extended Protocol Unit (EPU) for Classes T0 through T3 with all mandatory and optional commands, and the Advanced Protocol Unit (APU) for Classes T4 and T5. Its Transport function supporting 1 or 2 physical data channels with up to 16 data channel clients each, support for both 4-pin and 2-pin interface configurations, and all mandatory and optional scan formats (JScan, MScan, OScan, and SScan) give debug infrastructure SoC teams a production-tested, spec-complete Compact TAP implementation.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized class and topology architecture and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
