SmartDV’s cJTAG (IEEE 1149.7) Verification IP is built to verify compact JTAG implementations for debug and test access in space- and pin-constrained designs. Fully compliant with the IEEE 1149.7 specification, it enables accurate simulation of two-wire JTAG topologies and advanced debug features in modern SoCs.

The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with methodologies such as UVM, OVM, and VMM. It is simulator-independent and compatible with all leading EDA vendors’ simulators, ensuring broad toolchain support.

Featuring configurable master and slave agents, protocol checkers, scoreboards, and comprehensive coverage metrics, SmartDV’s cJTAG VIP accelerates testbench development and ensures protocol compliance. It is ideal for verifying low-pin-count debug and test infrastructure in automotive, mobile, and embedded applications.