SmartDV’s cJTAG Verification IP is a comprehensive solution for verifying the IEEE 1149.7 Compact JTAG interface, a reduced-pin and enhanced-functionality Test Access Port standard providing complete backward compatibility with IEEE 1149.1 while significantly extending test and debug capabilities for modern SoC designs. Fully compliant with IEEE 1149.7-2022, it supports complete verification of TAP.7 controller and TAP instruction and data generator components across all six TAP.7 capability classes T0 through T5, both 4-pin and 2-pin interface configurations, all mandatory and optional scan formats, and all EPU and APU commands.
SmartDV’s cJTAG VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive scan format support across JScan, MScan, OScan, and SScan, all scan register types, user-defined instruction and register extensibility, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s cJTAG VIP enables verification teams to thoroughly validate compact JTAG test and debug interfaces for mobile, automotive, IoT, and complex SoC applications requiring reduced pin count and enhanced debug functionality.
