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Overview

SmartDV’s I2C Slave IP is a silicon-proven, fully featured Inter-Integrated Circuit bus slave solution purpose-built for SoC designs requiring reliable, standards-compliant target-side I2C connectivity across embedded, IoT, automotive, and consumer electronics applications. Fully compliant with I2C v7.0 (NXP UM10204), it delivers complete I2C slave functionality with Start, repeated start, and stop support for all possible transfers, across Standard-mode, Fast-mode, Fast-mode Plus, and High-speed mode operation.

Designed for the practical integration requirements of modern I2C-based peripheral SoC designs, the IP supports 7-bit and 10-bit addressing and complete General Call address handling for standards-compliant slave-side operation across the full range of I2C bus speeds.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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I2C Slave
Key Features
  • Full I2C Slave Functionality – Complete slave implementation per I2C v7.0 with Start, repeated start, and stop support for all possible transfer types
  • All Standard Speed Modes – Standard-mode (100 kbit/s), Fast-mode (400 kbit/s), Fast-mode Plus (1 Mbit/s), and High-speed mode (3.4 Mbit/s)
  • Dual Addressing Modes – 7-bit and 10-bit slave addressing for broad I2C system compatibility
  • General Call Address Handling – Complete General Call address handling for standards-compliant broadcast command support
  • Clock Stretching Support – Slave-side clock stretching for flexible response timing under variable processing latency
  • Multi-Master Bus Compatibility – Full compatibility with single-master and multi-master I2C bus topologies
Compliance and Compatibility
  • Fully compliant with I2C v7.0 specification (NXP UM10204, October 2021)
  • Uses current NXP terminology: controller-target relationship (formerly master-slave)
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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