UFS VIP

Simulation

Overview

SmartDV’s UFS (Universal Flash Storage) 5.0 Verification IP is a comprehensive verification solution for validating Host and Device functionality across all layers of the UFS protocol stack. Fully compliant with JEDEC JESD220H (UFS 5.0) and UFSHCI JESD223G, it supports the complete UFS architecture including the UFS Command Set Layer (UCS), UFS Transport Protocol Layer (UTP), and UFS Interconnect Layer (UIC), and is backward compatible with UFS 4.1, 4.0, 3.1, 3.0, and 2.1.

SmartDV’s UFS 5.0 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With support for the full UFS protocol stack including integrated MIPI UniPro and M-PHY verification, comprehensive error injection, functional coverage, and a complete regression test suite, SmartDV’s UFS 5.0 VIP enables verification teams to thoroughly validate storage interface designs for mobile, automotive, AI, and high-performance embedded applications.

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UFS VIP

Benefits

Full Host and Device Functionality – Supports complete UFS Host and Device operation including device enumeration and discovery, boot mode, multiple LUNs with partition management, enhanced user data areas, boot and RPMB partitions, and task and power management operations.
Comprehensive UFS Interconnect Layer Verification – Includes integrated MIPI UniPro and M-PHY VIP for UIC layer verification, with support for UniPro 1.41 through 3.0 and MIPI M-PHY 3.0 through 6.0, covering all PWM and HS gears, 1 and 2 lane configurations, hibernate entry/exit, lane mapping and reverse lane mapping, and all DME commands.
UFS 5.0 and Latest Protocol Support – Supports HS-G6 speed, TX Equalization Configuration, Device Attestation Buffer, Multi-circular Queue (MCQ) in UFSHCI, Fast Recovery Mode, Out of Order support, and advanced RPMB as introduced in UFS 4.x and 5.x specifications.
Flexible VIP Interface Access – Supports verification at multiple interface levels including M-PHY Serial, M-PHY RMMI, and UniPro CPort, with RMMI bus widths of 10, 20, 40, 80, and 160 bits per lane and CPort interface widths up to 256 bits.
Advanced UniPro 3.0 Features – Covers HS-G6, PAM-4, Forward Error Correction, TFS frames, data scrambling, gray coding, pre-coding, lane synchronization, replay mechanism, link equalization and training, and HS-LSS for complete next-generation interconnect verification.
Data Security and Protection Verification – Validates secure operations including purge and erase, permanent and power-on write protection, reliable write, and signed RPMB access per UFS 3.1 and later specifications.
Host Performance Booster and Write Booster Support – Verifies HPB version 1.0 and 2.0 per JESD220-3 and JESD220-3A, Write Booster, Deep Sleep power mode, Performance Throttling Event Notification, and Unified Memory Extension per JESD220-1A.
Robust Error Injection and Protocol Checking – Supports error injection and detection at all UFS protocol layers, advanced L1.5, L2, and CPort error injection, L1.5 error recovery, L2 preemption, and PA re-initialization, with event notifications for transactions, warnings, and protocol violations.
Complete Verification Infrastructure – Provides a full regression test suite covering all UFS specification features, functional coverage analysis, constraints randomization, and callbacks in both Host and Device for user-defined event handling and monitoring.

Compliance and Compatibility

Fully compliant with JEDEC JESD220H (UFS 5.0); backward compatible with UFS 4.1, 4.0, 3.1, 3.0, and 2.1
Compliant with UFSHCI JESD223G (version 5.0)
Compliant with UFS Unified Memory Extension JESD220-1A (version 1.1)
Compliant with UFS Host Performance Booster Extension JESD220-3A (version 2.0)
Compliant with MIPI M-PHY v6.0 and MIPI UniPro v3.0 for UFS Interconnect Layer
Supports UniPro versions 1.41, 1.6, 1.8, 2.0, and 3.0
Supports MIPI M-PHY versions 3.0, 4.1, 5.0, and 6.0
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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Related Products

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