SmartDV’s UFS (Universal Flash Storage) 5.x Host IP is a next-generation storage interface solution engineered for the most demanding SoC applications in mobile, automotive, AI/ML, and high-performance embedded systems. Fully compliant with JEDEC UFS 5.0 specifications, MIPI M-PHY v6.0, and MIPI UniPro v3.0 standards, it delivers unprecedented throughput and ultra-low latency for UFS 5.0-compatible memory devices. With sequential read and write speeds of up to 10.8 GB/s over dual M-PHY lanes, it sets a new performance benchmark for next-generation storage subsystems.
As AI workloads push storage bandwidth requirements to new extremes, the UFS 5.x Host IP gives SoC teams the headroom to meet those demands without compromise. Its support for HS-Gear6, Multiple Circular Queue mode, and inline cryptographic hashing positions it as a strategic choice for teams building the next generation of AI-enabled mobile, automotive, and edge devices.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean SoC interface options enable fast integration and rapid design bring-up across a wide range of process nodes and target applications.
