MIPI UniPro VIP

Simulation

Overview

SmartDV’s MIPI UniPro Verification IP is a comprehensive solution for verifying the complete UniPro protocol stack, from the physical layer through the transport layer, including integrated MIPI M-PHY support. Fully compliant with MIPI UniPro v3.0 and MIPI M-PHY v6.0 and backward compatible with UniPro 1.41, 1.6, 1.8, and 2.0 and M-PHY 3.0, 4.1, and 5.0, it provides thorough verification coverage across all UniPro layers including the PHY Adapter Layer, Data Link Layer, Network Layer, and Transport Layer, along with complete DME functionality.

SmartDV’s MIPI UniPro VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With multi-lane M-PHY support, extensive error injection across all protocol layers, fine-grain flow control testing, functional coverage, and a complete test suite, SmartDV’s MIPI UniPro VIP enables verification teams to thoroughly validate UniPro-based interconnect designs for mobile, automotive, and high-performance embedded applications.

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MIPI UniPro VIP

Benefits

Complete Protocol Stack Coverage – Verifies all UniPro layers including the PHY Adapter Layer, Data Link Layer, Network Layer, and Transport Layer, with support for data control at each layer for efficient debug and full DME functionality.
Comprehensive M-PHY Physical Layer Support – Supports M-PHY Serial and RMMI interfaces with bus widths of 10, 20, 40, 80, and 160 bits per lane, up to four M-PHY lanes, all power modes, Type-I support, clock recovery in HS mode, lane-to-lane skew, and transmission and reception of encoded PHY symbols including IDLE symbol detection and re-initialization.
PHY Adapter Layer Verification – Covers lane distribution and merging in multi-lane ports, UniPro power management operating modes, TX path re-initialization, transmit lane connect and disconnect, all types of lane mapping, error injection in LSS and PA layer operations, and PHY test mode.
Data Link Layer Verification – Supports data frames and control frames, frame composition and decomposition, buffering, frame preemption and preemption error injection, flow control fine grain testing, priority-based arbitration for two traffic classes, L2 error injection for all cases including PA initialization errors, and protocol error detection.
Network and Transport Layer Verification – Covers packet composition and decomposition, traffic class support, multiple connections and segments in the L4 layer, all valid segment sizes, end-to-end flow control, connection management, CPort arbitration at both segment and packet levels, CPort buffer-based E2E checking, and L4 test feature support.
Extensive Error Injection and Detection – Supports error injection and detection across all protocol layers including Layer 3, Layer 2, PACP frames, LSS sequences, and M-PHY errors such as disparity errors, invalid control characters, invalid sync sequencer errors, timeout conditions, and CRC errors.
Advanced UniPro 2.0 and 3.0 Features – Covers HS-G5 and HS-G6 gear support, linkstartup sequence in HS and LS modes, L2 buffer extension, RMMI bus width extension to 80 and 160 bits per lane, PA capability user data in PACP CAP IND frames, extended save time attributes, scrambler and SKIP pattern insertion, Marker 2 extension, and periodic deskew and filler injection.
Complete Verification Infrastructure – Provides a full test suite covering every UniPro specification feature, functional coverage for all functional conditions, constraints randomization, status counters for bus events, and callbacks in transmitter, receiver, and monitor for user-defined event handling and protocol violation notification.

Compliance and Compatibility

Fully compliant with MIPI UniPro v3.0; backward compatible with UniPro 2.0, 1.8, 1.6, and 1.41
Fully compliant with MIPI M-PHY v6.0; backward compatible with M-PHY 5.0, 4.1, and 3.0
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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