SmartDV’s MIPI M-PHY Verification IP is a comprehensive solution for verifying the M-PHY physical layer interface across all operating modes, gear configurations, and interface types. Fully compliant with MIPI M-PHY v6.0 and backward compatible with v5.0, v4.1, and v3.0, it supports both serial and protocol layer interfaces, Type-I and Type-II operations, all PWM gears (0 through 7), all HS gears (1 through 4), and multi-lane configurations with inter-lane skew insertion and detection.
SmartDV’s MIPI M-PHY VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With extensive 8b/10b error injection, clock recovery modeling, fine-grain timing control, test pattern generation, functional coverage, and a complete test suite, SmartDV’s MIPI M-PHY VIP enables verification teams to thoroughly validate M-PHY physical layer designs for mobile, automotive, storage, and high-performance embedded applications.
