IEEE 1149.7 DTS Adapter IP

Design IP

Overview

SmartDV’s IEEE 1149.7 DTS (Debug and Test System) Adapter IP enables seamless communication between on-chip debug components and external test equipment through a compact IEEE 1149.7-compliant interface. It serves as a bridge between the system’s debug infrastructure and external tools, simplifying access, monitoring, and control in complex SoC environments.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. With features such as dynamic port addressing, multi-device support, and low-pin operation, the DTS Adapter IP is ideal for integrating scalable debug access into resource-constrained designs.

Benefits

Comprehensive Debug and Test Access – Implements full IEEE 1149.7 DTS Adapter functionality, enabling efficient connection between external debug systems and on-chip logic for both test and trace operations
Complete Class Coverage – Supports IEEE 1149.7 TAP.7 capability classes T0 to T5, ensuring broad interoperability across legacy JTAG and compact JTAG environments
Advanced Protocol Support – Includes Reset and Escape sequence generation, Extended Protocol Unit (EPU) for classes T0–T3 with all mandatory and optional EPU commands, and Advanced Protocol Unit (APU) for classes T4 and T5
High-Efficiency Transport Layer – Supports one or two Physical Data Channels (PDCs), each providing access to up to 16 Data Channel Clients (DCCs) for optimized multi-device communication
Flexible Scan Operation – Provides full support for all mandatory and optional scan formats (JScan, MScan, OScan, and SScan) with Data Register, Instruction Register, Control Register, and Zero-Bit Scans
Multi-Topology Flexibility – Operates across Series (Class T0–T5), Star-4 (Class T3–T5), and Star-2 (Class T4–T5) scan topologies for versatile SoC debug configurations
Compact and Customizable Integration – Supports both 2-pin and 4-pin Compact JTAG interfaces as specified in IEEE 1149.7, and can be extended with user-defined instructions and registers for specific debug or test needs

Compliance and Compatibility

Fully compliant with IEEE 1149.7 Compact JTAG (cJTAG) Standard
Compatible with all major EDA synthesis, simulation, and linting flows

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