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IEEE 1149.7 Compact TAP IP
Design IP
Overview

SmartDV’s IEEE 1149.7 Compact TAP IP offers a compact, low-pin-count solution for test, debug, and instrumentation, fully compliant with the IEEE 1149.7 standard. Ideal for modern SoC designs, it enables advanced access to embedded devices in power-sensitive and space-constrained applications across automotive, industrial, and consumer electronics.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. It supports key features such as star topology, power-aware test modes, and backward compatibility with IEEE 1149.1, and can be easily integrated into existing debug infrastructures, providing a seamless path for robust test and diagnostic capabilities.

IEEE 1149.7 Compact TAP
Benefits
  • Compact and Scalable Debug Architecture – Implements the IEEE 1149.7 (Compact JTAG) standard with reduced pin count and advanced debug functionality over traditional JTAG interfaces
  • Comprehensive Class Support – Supports TAP.7 capability classes T0 to T5, including optional Reset and Selection Unit (RSU) for T0 features, Extended Protocol Unit (EPU) for T0–T3, and Advanced Protocol Unit (APU) for T4 and T5
  • Flexible Data Transport – Supports one or two Physical Data Channels (PDCs), each accommodating up to 16 Data Channel Clients (DCCs), enabling efficient multi-device communication
  • Multiple Scan Formats and Functions – Provides full support for JScan, MScan, OScan, and SScan formats, with dedicated support for Data Register, Instruction Register, Control Register, and Zero-Bit Scans
  • Versatile Scan Topologies – Compatible with Series (Class T0–T5), Star-4 (Class T3–T5), and Star-2 (Class T4–T5) topologies for optimal chain or star connectivity
  • Extensible Instruction Set – Can be easily extended with user-defined instructions and registers, allowing adaptation to custom test and debug requirements
  • Optimized Interface Flexibility – Supports both 2-pin and 4-pin Compact JTAG interfaces as defined in IEEE 1149.7 for reduced pin utilization and simplified routing
Compliance and Compatibility
  • Fully compliant with IEEE 1149.7 Compact JTAG (cJTAG) Standard
  • Compatible with all major EDA synthesis, simulation, and linting flows