SmartDV’s eSPI Target to LPC Bridge IP is a silicon-proven, fully featured protocol bridge solution purpose-built for SoC designs requiring seamless connectivity between eSPI controllers and legacy Low Pin Count peripheral devices across embedded controller and Super-I/O applications. Compliant with the eSPI Interface Base Specification Revision 1.6 and LPC Interface Specification Revision 1.1, it converts eSPI Peripheral Channel transactions into LPC Memory write and read instructions, enabling full LPC host capability while presenting a standards-compliant eSPI target interface to the eSPI controller.
Designed for the practical integration requirements of legacy peripheral migration to eSPI-based embedded controller designs, the IP implements a complete eSPI target interface supporting Single, Dual, and Quad eSPI data lines, all three eSPI reset types, TX and RX operation across the Command, Turn-Around, and Response phases, Peripheral and Virtual Wires channels, and CRC checking, alongside a full LPC Host interface with Serial IRQ support, variable wait-state support, and complete LPC I/O and Memory read/write frame handling. Its comprehensive error detection and handling gives embedded controller SoC teams a production-tested bridge solution for legacy Super-I/O peripheral integration in modern eSPI-based platforms.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration across a wide range of process nodes and target applications.
