SmartDV’s eSPI Target IP is a silicon-proven, fully featured Enhanced Serial Peripheral Interface target solution purpose-built for SoC designs requiring reliable, standards-compliant target-side eSPI connectivity across embedded controller, Super-I/O, and BMC peripheral applications. Fully compliant with the eSPI Interface Base Specification Revision 1.6, it delivers complete target functionality in Single, Dual, and Quad I/O modes with Target-triggered transaction support and Power Management Event handling.
Designed for the practical integration requirements of modern eSPI-based embedded peripheral designs, the IP supports all three eSPI reset types including Controller-to-Target reset, Target-to-Controller reset, and in-band reset command, the complete Command, Turn-Around, and Response transaction phases, Interrupts and Alert signaling, and all four eSPI channels: Peripheral, Virtual Wires, Out-of-Band, and Run-time Flash Access. Its full TX and RX operation per specification and Target-triggered transaction capability give embedded peripheral SoC teams a production-tested eSPI target implementation.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized channel architecture and clean host interface enable fast integration across a wide range of process nodes and target applications.
