SmartDV’s eSPI Controller IP is a silicon-proven, fully featured Enhanced Serial Peripheral Interface controller solution purpose-built for SoC designs requiring reliable, standards-compliant controller-side eSPI connectivity across embedded controller, BMC, and Super-I/O interconnect applications. Fully compliant with the eSPI Interface Base Specification Revision 1.6, it delivers complete controller functionality in Single, Dual, and Quad I/O modes across Single Controller-Single Target and Single Controller-Multiple Target system topologies.
Designed for the practical integration requirements of modern eSPI-based embedded system designs, the IP supports all three eSPI reset types including Controller-to-Target reset, Target-to-Controller reset, and in-band reset command, configurable baud rate selection, the complete Command, Turn-Around, and Response transaction phases, and all four eSPI channels: Peripheral, Virtual Wires, Out-of-Band, and Run-time Flash Access. Its full TX and RX operation per specification gives embedded controller SoC teams a production-tested eSPI controller implementation for reliable multi-target system interconnect.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized channel architecture and clean host interface enable fast integration across a wide range of process nodes and target applications.
