SmartDV’s eSPI Verification IP is a comprehensive solution for verifying the Enhanced Serial Peripheral Interface, Intel’s low pin count successor to the Legacy LPC bus for connecting Embedded Controllers, Baseboard Management Controllers, and Super I/O devices to platform chipsets. Fully compliant with the Intel eSPI Interface Base Specification Revision 1.6 and backward compatible with Revision 1.5 and earlier versions, it supports complete verification of eSPI Controller and Target components across 2-wire and 4-wire interfaces, single, dual, and quad operating modes, all four eSPI channels, and the complete transaction phase sequence covering Command, Turn-Around, and Response phases for both Controller-initiated and Target-triggered transactions.
SmartDV’s eSPI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive error detection and handling for both Controller and Target-detected errors, CRC checking, power management event support, in-band reset, interrupt and alert handling, backdoor data initialization, configurable FIFO and standard device modes, built-in functional coverage, and a complete test suite, SmartDV’s eSPI VIP enables verification teams to thoroughly validate eSPI interface designs for client and server platform EC, BMC, SIO, and embedded controller applications.
