LPC VIP

Simulation

Key Features Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s LPC Verification IP is a comprehensive solution for verifying the Intel Low Pin Count interface, a low-bandwidth serial bus connecting legacy I/O peripherals to host chipsets in PC and embedded systems. Fully compliant with the Intel LPC Interface Specification Revision 1.1, it supports complete verification of LPC host and device components across all six defined cycle types at up to 33 MHz, covering memory, I/O, DMA, bus master memory and I/O, and firmware memory read and write operations, with variable wait state support, serial interrupt handling, LDRQ request support, and wakeup and power state management.

SmartDV’s LPC VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive error injection, bus-accurate timing and protocol violation detection, built-in functional coverage, and a complete test suite, SmartDV’s LPC VIP enables verification teams to thoroughly validate LPC interface designs for PC chipsets, Super I/O devices, BMC controllers, embedded controllers, TPM modules, and server management applications.

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LPC VIP

Key Features

Full LPC Host and Device Support – Provides complete LPC host and device functionality with the host capable of generating all defined LPC transaction types and the device capable of responding to all defined LPC transaction types, operating at up to 33 MHz clock frequency across the LAD[3:0] multiplexed 4-bit bus.
Comprehensive Cycle Type Coverage – Supports all six LPC cycle types including memory read and write, I/O read and write, DMA read and write, bus master memory read and write, bus master I/O read and write, and firmware memory read and write, providing complete LPC transaction plane verification.
Bus Management and Power State Support – Supports LDRQ DMA request signaling, serial interrupt generation and detection via SERIRQ, variable number of wait states for peripheral latency modeling, wakeup event handling, and all defined LPC power state transactions.
Comprehensive Error Injection and Detection – Supports injection of all defined LPC error conditions enabling thorough protocol violation and error recovery verification across all cycle types and bus states.
Robust Protocol Checking and Monitoring – Provides continuous monitoring of LPC bus behavior during simulation, covering protocol errors, timing violations, and all significant bus events including transactions, warnings, and protocol violations.
Complete Verification Infrastructure – Provides a full test suite covering all LPC Revision 1.1 specification features, built-in functional coverage analysis, and protocol error and timing violation detection and notification across all LPC operating conditions.

Compliance and Compatibility

Fully compliant with Intel LPC Interface Specification Revision 1.1 (August 2002)
Supports all six LPC cycle types at up to 33 MHz
Supports LDRQ, SERIRQ, and LPC power management signaling
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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