SmartDV’s Embedded DisplayPort Verification IP is a comprehensive solution for verifying the embedded display interface used in laptops, tablets, automotive displays, and other embedded panel applications. Fully compliant with VESA eDP v1.5a and backward compatible with eDP 1.5, 1.4b, 1.4, and 1.3, and based on DisplayPort specifications 1.2 through 2.0, it supports complete verification of eDP source and sink devices across up to four lanes, all main link and AUX link functionality, HPD-based link training, Panel Self Refresh including PSR2 and Panel Replay, Multi-SST Operation, Display Stream Compression, Forward Error Correction, and Advanced Link Power Management.
SmartDV’s eDP VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive color format and video packing support, HDCP 1.3, 2.2, and 2.3 content protection, ECC and error injection, GTC-based video timing synchronization, display backlight control via DPCD registers, interlane skew insertion and deskew, dynamic scrambler control, built-in functional coverage, and a complete test suite, SmartDV’s eDP VIP enables verification teams to thoroughly validate embedded display interface designs for laptop PCs, tablets, automotive displays, and high-resolution embedded panel applications.