SmartDV’s eDP Receiver IP is a silicon-proven, fully featured Embedded DisplayPort receiver solution purpose-built for SoC designs requiring reliable, standards-compliant display panel signal reception across mobile, laptop, tablet, and embedded industrial display applications. Supporting Display Port v1.3 and Embedded Display Port v1.5a specifications, it delivers complete eDP receiver functionality with support for up to 1, 2, or 4 lanes, 10/20/40/80-bit input data width, and 1/2/4/8 pixels per clock, providing a proven, production-ready embedded display panel receiver for panel timing controller and display driver SoC designs.
Designed for the practical integration requirements of modern embedded display panel SoC designs, the IP supports Main Link, AUX Channel, and Hot Plug functionality, AUX CH access to DPCD and I2C-over-AUX for EDID/EEPROM, AUX Pin Swap, HPD Interrupt Function, AUX channel operation at 1 Mbps with up to 16 bytes burst data, both Default and Enhanced framing modes, and all standard DP color formats. Its Content Production Alternate Scramble Seed Reset, Panel Self Refresh functionality, Multi SST operation across multiple lane and link configurations, and Full and Fast Link Training give mobile and laptop SoC teams a production-tested eDP receiver for power-efficient embedded display connectivity.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane and link rate architecture and clean host interface enable fast integration across a wide range of process nodes and target applications.
