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Overview

SmartDV’s eDP Transmitter IP is a silicon-proven, fully featured Embedded DisplayPort transmitter solution purpose-built for SoC designs requiring reliable, standards-compliant display panel connectivity across mobile, laptop, tablet, and embedded industrial display applications. Supporting Display Port v1.3 and Embedded Display Port v1.5a specifications, it delivers complete eDP transmitter functionality with dynamic support for 1, 2, or 4 lanes, configurable output data widths, and configurable pixels per clock, providing a proven, production-ready embedded display interface for panel-integrated SoC designs.

Designed for the practical integration requirements of modern embedded display panel SoC designs, the IP supports Main Link, AUX Channel, and Hot Plug functionality, AUX CH access to DPCD and I2C-over-AUX for EDID/EEPROM, AUX Pin Swap, both Default and Enhanced framing modes, Main Stream Attribute packets, and all standard DP color formats from RGB and YCbCr variants through Y-only and RAW formats. Its Seamless Display Refresh Rate Switching, Panel Self Refresh functionality, Multi SST operation across multiple lane and link configurations, and optional HDCP v2.3 authentication give mobile and laptop SoC teams a production-tested eDP transmitter for power-efficient embedded display connectivity.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane and link rate architecture and clean host interface enable fast integration across a wide range of process nodes and target applications.

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eDP Transmitter
Key Features
  • Full eDP Transmitter Functionality – Complete transmitter implementation supporting DP v1.3 and eDP v1.5a with dynamic 1, 2, or 4 lane support and configurable output data width and pixels per clock
  • Comprehensive Color Format Support – RGB (18-48 bpp), YCbCr 4:4:4/4:2:2/4:2:0, Y-only, and RAW formats with configurable bit depth per DP specifications
  • Complete SDP Support – Audio Timestamp, Audio Stream, Extension, Audio Copy Management, ISRC, VSC, Camera SDP 8-15, and Info Frame Secondary Data Packet formats
  • Panel Power Features – Seamless Display Refresh Rate Switching (SDRRS) and Panel Self Refresh (PSR) functionality for power-efficient mobile and laptop display operation
  • Multi SST Operation – Multiple SST link configurations (2×1, 2×2, 4×1) for flexible panel bandwidth aggregation
  • DP Link Rate Support – RBR (1.6 Gbps), HBR (2.7 Gbps), HBR2 (5.4 Gbps), and HBR3 (8.1 Gbps) link rates
  • Optional HDCP Support – Optional HDCP v2.3 support with full authentication and bypass authentication modes
Compliance and Compatibility
  • Compliant with DisplayPort v1.3 and Embedded DisplayPort v1.5a specifications; backward compatible with eDP v1.4b
  • Optional support for HDCP v2.3 content protection
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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