SmartDV’s VESA DSC Decoder IP is a silicon-proven, fully featured Display Stream Compression decoder solution purpose-built for SoC designs requiring low-latency, visually lossless display decompression across mobile, automotive, AR/VR, and high-resolution display applications. Fully compliant with VESA DSC v1.2b and backward compatible with DSC v1.2a, v1.2, and v1.1, it delivers complete DSC decoder functionality supporting all four DSC coding schemes, comprehensive color format coverage, up to 24-slice parallel decoding, and display resolutions up to 8K — providing a proven, production-ready DSC decoder for the most demanding display interface SoC designs.
Verified against the VESA DSC 1.2a C reference model using sample images, the IP implements all four DSC prediction modes — Modified Median-Adaptive Prediction (MMAP), Block Prediction (BP), Midpoint Prediction (MPP), and Indexed Color History (ICH) — alongside PPS 128-byte block decoding, input buffering compatible with HDMI 2.1, MIPI DSI, and DisplayPort transport streams, and programmable compressed bit rates from 6 bpp for 4:2:0 to 8 bpp and higher for other formats. Its support for 8, 10, 12, 14, and 16 bits per component and up to 24 parallel slice decoding gives display SoC teams a production-tested, spec-complete DSC decoder that handles the full range of modern high-resolution display compression configurations.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized slice architecture, transport stream input buffering, and clean host interface enable fast integration and confident design bring-up across a wide range of advanced display process nodes and target applications.
