SmartDV’s MIPI DSI-2 Receiver IP is a silicon-proven, high-performance display interface solution engineered for SoC designs requiring reliable, high-bandwidth display data reception across mobile, automotive, gaming, and high-performance embedded applications. Fully compliant with MIPI DSI-2 v2.2, MIPI D-PHY v3.0, MIPI C-PHY v3.1, DPI-2 v2.0, DBI-2, and DCS v2.1, it delivers complete receiver-side DSI-2 functionality with support for both D-PHY and C-PHY physical layers, enabling data rates up to 9 Gbps per lane on D-PHY and up to 3 Gsps per trio on C-PHY.
Designed to address the full breadth of modern display reception requirements, the IP supports both Video and Command modes, all BTA bidirectional turnaround commands, forward and reverse communication, and an extensive pixel format library spanning YCbCr and RGB data types. Its comprehensive error detection and correction capabilities, interrupt support, and deskew mechanism make it a robust, production-ready solution for the most demanding display subsystem designs across mobile, automotive, and ultra-high-definition applications.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its PPI interface for seamless C-PHY and D-PHY integration, DPI-2 and DBI interface support, and programmable interrupt events enable fast integration and confident design bring-up across a wide range of process nodes and display applications.
