SmartDV’s MIPI CSI-2 Receiver IP is a silicon-proven, high-performance camera interface solution engineered for SoC designs requiring reliable, high-bandwidth image data reception across mobile, automotive, AI/ML, industrial, and medical imaging applications. Fully compliant with MIPI CSI-2 v4.2, MIPI D-PHY v3.0, and MIPI C-PHY v3.1, it delivers complete receiver-side CSI-2 functionality with support for both D-PHY and C-PHY physical layers, enabling data rates up to 9 Gbps per lane on D-PHY and up to 3 Gsps per trio on C-PHY.
Designed to address the full breadth of modern imaging requirements, the IP supports an extensive pixel format library spanning RAW, RGB, and YUV data types, up to 32 interleaved virtual channels on C-PHY, multi-lane configurations up to 8 lanes on D-PHY, and advanced features including LRTE, Alternate Low Power mode, data descrambling, and deskew mechanisms. Its comprehensive error detection and correction capabilities including 6-bit ECC for packet headers and 16-bit checksum for active data make it a robust, production-ready solution for the most demanding camera subsystem designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its PPI interface for seamless C-PHY and D-PHY integration, pixel-level ISP interface with HSYNC, VSYNC, DATA, and DATA VALID signals, and programmable synchronization and interrupt events enable fast integration and confident design bring-up across a wide range of process nodes and imaging applications.
