SmartDV’s MIPI DSI-2 Verification IP is a comprehensive solution for verifying the high-bandwidth link between host processors and display modules across the complete MIPI Display Serial Interface family. Fully compliant with MIPI DSI-2 v2.2 (July 2024) and MIPI DSI v1.3.2, and supporting both MIPI C-PHY v3.1 and D-PHY v3.6 physical layers, it provides complete verification of DSI and DSI-2 transmitter and receiver components across all lane configurations up to 8 lanes for D-PHY and 4 trios for C-PHY, covering all short and long packet types, high-speed and low-power transmission modes, Display Stream Compression, DBI and DCS command set support, Link Distribution Function, data scrambling, skew calibration, all BTA commands, and the PHY-Protocol Interface for both physical layer implementations.
SmartDV’s MIPI DSI-2 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive data rate coverage from 80 Mbps to 12 Gbps per lane in D-PHY and up to 5.7 Gbps per trio in C-PHY, video-to-command mode, adaptive refresh, Video Hybrid Mode, timeout detection and error injection, fine-grain timing control, built-in functional coverage, and a complete test suite, SmartDV’s MIPI DSI-2 VIP enables verification teams to thoroughly validate display serial interface designs for smartphones, tablets, automotive infotainment, AR/VR headsets, gaming displays, and embedded display applications.
