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Overview

SmartDV’s MIPI CSI-2 Verification IP is a comprehensive solution for verifying the world’s most widely implemented embedded camera and imaging interface, providing complete verification of the MIPI Camera Serial Interface 2 protocol across both C-PHY and D-PHY physical layers. Fully compliant with MIPI CSI-2 v4.2 (December 2025) and backward compatible with all previous versions including v4.1, v4.0, v3.0, v2.1, v2.0, and v1.0 through v1.3, it supports complete verification of CSI-2 transmitter and receiver components across all lane configurations, all virtual channel identifiers with virtual channel extension, all pixel formats from 6 to 24 bits per pixel, all short and long packet types, data scrambling, skew calibration, Smart Region of Interest, Latency Reduction and Transport Efficiency, RAW data compression, and the PHY-Protocol Interface for both C-PHY and D-PHY implementations.

SmartDV’s MIPI CSI-2 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive interleaved data transmission support, forward escape and ULPM on all data lanes, glitch injection across multiple lanes, comprehensive error injection and detection, control bus support via CCI, built-in functional coverage, and a complete test suite, SmartDV’s MIPI CSI-2 VIP enables verification teams to thoroughly validate camera serial interface designs for mobile, automotive ADAS, AR/VR, IoT, medical imaging, industrial machine vision, and drone applications.

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MIPI CSI-2 VIP
Key Features
  • Full CSI-2 TX and RX Support with C-PHY and D-PHY – Provides complete MIPI CSI-2 transmitter and receiver functionality with support for both MIPI C-PHY and D-PHY physical layers, all lane configurations, PHY-Protocol Interface, high-speed mode of operation, forward escape and ULPM on all data lanes, and CCI control bus for bidirectional command and control.
  • Comprehensive Packet and Pixel Format Coverage – Supports all types of short packets including frame start, frame end, line start, and line end synchronization packets, all types of long packets covering all pixel formats from 6 to 24 bits per pixel, RAW data compression, and all virtual channel identifiers with virtual channel extension field as defined in CSI-2 v2.0 and later.
  • Advanced CSI-2 Features – Supports data scrambling per CSI-2 v2.0, skew calibration for high-speed lane alignment, Smart Region of Interest for partial frame transmission, Latency Reduction and Transport Efficiency for reduced transmission overhead, Multi-Pixel Compression for advanced image sensor data reduction, RAW28 pixel encoding for high-dynamic-range automotive imaging, and Always-On Sentinel Conduit for ultra-low-power machine vision as introduced in CSI-2 v4.0.
  • Interleaved Data Transmission Support – Supports all defined methods for interleaving transmission of different image data formats including interleaved data transmission using data type value and using virtual channels, covering both packet-level interleaved data transmission and frame-level interleaved data transmission.
  • Comprehensive Error Injection and Detection – Supports injection and detection of all defined CSI-2 error types including SoT errors, sync errors, word count errors, sync length errors, checksum errors, and ECC errors, along with glitch injection and detection across multiple lanes for thorough physical and protocol layer fault simulation.
  • C-PHY v3.1 and D-PHY v3.6 Physical Layer Support – Supports MIPI C-PHY v3.1 including 18-wire-state mode for 30-35% performance improvement per lane and reduced EMI, and MIPI D-PHY v3.6 including D-PHY ECM support as added in CSI-2 v4.2, covering the full range of physical layer configurations for both standalone and combo C/D-PHY implementations.
  • Complete Verification Infrastructure – Provides a full test suite covering all MIPI CSI-2 v4.2 specification features, built-in functional coverage analysis, constraints randomization, status counters for bus events, and callbacks in transmitter, receiver, and monitor for user-defined data processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with MIPI CSI-2 v4.2 (December 2025); backward compatible with v4.1, v4.0, v3.0, v2.1, v2.0, and v1.0 through v1.3
  • Supports MIPI C-PHY v3.1 (December 2025) and MIPI D-PHY v3.6 (September 2025)
  • Supports standalone C-PHY, D-PHY, and combo C/D-PHY configurations
  • Supports all virtual channel identifiers with virtual channel extension
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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