SmartDV’s DisplayPort 2.x Receiver IP is a fully featured DisplayPort receiver solution purpose-built for SoC designs requiring high-bandwidth, standards-compliant display video reception across AR/VR, high-resolution monitor, and next-generation display applications. Fully compliant with DisplayPort 2.1a and backward compatible with DisplayPort 2.0 and 1.4a, it delivers complete Sink-side receiver functionality supporting Ultra High Bit Rate (UHBR) link rates alongside all legacy DisplayPort link rates, using the same 128b/132b channel coding shared with USB4 for maximum bandwidth efficiency.
Designed for beyond-8K and multi-display applications, the IP supports UHBR10, UHBR13.5, and UHBR20 link rates delivering up to 77.37 Gbps of payload bandwidth across four lanes, alongside RBR, HBR, HBR2, and HBR3 legacy rates, AUX Channel access to DPCD and I2C-over-AUX, Main Stream Attribute packet decoding, and comprehensive Secondary Data Packet support. Its support for VESA DSC compressed video streams, HDCP content protection compatibility, and full and fast link training give display SoC teams a production-ready DisplayPort 2.x receiver suited for 8K, 16K, and high-refresh-rate VR display applications.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane and link rate architecture and clean host interface enable fast integration across a wide range of process nodes and target applications.
