SmartDV’s DisplayPort Verification IP is a comprehensive solution for verifying high-bandwidth digital display interfaces across the complete DisplayPort protocol stack. Fully compliant with VESA DisplayPort 2.1b and backward compatible with DisplayPort 2.1a, 2.0, 1.4a, and earlier versions, it supports complete verification of DisplayPort source and sink devices covering all UHBR and HBR link rates up to UHBR20, 8b/10b and 128b/132b channel coding, Single Stream Transport and Multi-Stream Transport, up to four lanes, all secondary data packet types, and the full range of link training, power management, and content protection features defined in the current DisplayPort specification.
SmartDV’s DisplayPort VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive audio and video format support, Display Stream Compression up to v1.2b, Panel Replay, Adaptive Sync, Advanced Link Power Management, LTTPR support in transparent and non-transparent modes, HDCP 1.3, 2.2, and 2.3 content protection, extensive error injection, built-in functional coverage, and a complete test suite, SmartDV’s DisplayPort VIP enables verification teams to thoroughly validate display interface designs for consumer electronics, PC, gaming, and high-performance embedded display applications.
