eDP Receiver IP

Design IP

Overview

SmartDV’s eDP (Embedded DisplayPort) Receiver IP is a high-performance solution tailored for advanced display interfaces across mobile, automotive, and embedded systems. It supports VESA Embedded DisplayPort specifications including eDP v1.3, v1.4, v1.4a, and v1.5, ensuring compatibility with the latest generation of embedded display technologies. Key features include support for Panel Self Refresh (PSR), Display Stream Compression (DSC) as per VESA DSC v1.2, and comprehensive AUX Channel protocol handling.

Designed for flexibility, the IP core is highly configurable to meet specific design requirements, supporting both ASIC and FPGA implementations while optimizing for area, power, and performance. Its modular and protocol-aware architecture enables seamless integration with SoCs and display subsystems, delivering robust and efficient video connectivity.

Benefits

High-Performance Embedded Display Interface – Supports up to 8K resolution over 1, 2, or 4 Main Link lanes with lane bonding and link rates up to HBR3 (8.1 Gbps per lane)
Wide Feature Set for Embedded Applications – Ideal for laptops, tablets, AR/VR, and automotive displays with support for Panel Self Refresh (PSR and PSR2), AUX channel, and deep sleep modes
Integrated Security and Compression – Supports HDCP 1.4/2.2 for content protection, Display Stream Compression (DSC) for bandwidth optimization, and Forward Error Correction (FEC) for improved signal integrity
Robust Video Data Handling – Implements symbol lock, lane deskew, clock recovery, and pixel extraction with seamless integration into video processing pipelines
Flexible Protocol Handling – Full support for DPCD register access, link training, and AUX transactions
Easy SoC Integration – Interfaces cleanly with standard buses like AXI, AHB, or APB and works with downstream display protocols such as HDMI or MIPI DSI

Compliance and Compatibility

Fully compliant with VESA Embedded DisplayPort (eDP) Specification, up to version 1.5
Supports DisplayPort Link Layer, AUX Channel, HDCP 1.4/2.2, DSC, FEC, and PSR/PSR2 standards
Compatible with all major EDA synthesis, simulation, and linting flows

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