SmartDV’s xSPI Master IP is a silicon-proven, fully featured eXtended Serial Peripheral Interface master solution purpose-built for SoC designs requiring high-performance, standards-compliant connectivity to Octal SPI flash memories and other xSPI-compatible devices across embedded, automotive, AI/ML, and high-performance computing applications. Fully compliant with JEDEC xSPI JESD251 v1.0, it delivers complete xSPI master functionality supporting Single, Dual, Quad, and Octal lane modes in both SDR and DDR configurations at data transfer rates up to 400 MT/s, with integrated DMA engine, XIP/AIP mode, and Auto Boot Mode — providing a proven, production-ready xSPI master for the most demanding flash storage SoC designs.
Designed to address the full breadth of xSPI integration requirements, the IP supports xSPI Profile 1.0 commands for non-volatile memory management, xSPI Profile 2.0 commands for universal read/write slave access, 1S-1S-1S and 8D-8D-8D protocol modes covering all Command, Address, Latency, and Data transaction phase configurations, Data Mask for write masking, Data Strobe for read transactions, Deep Power Down entry and exit, and legacy SPI device support on the same interface. Its inbuilt Host Controller Interface DMA engine and support for multiple slaves per interface port give SoC teams a production-tested, feature-complete xSPI master that handles the widest range of commercial xSPI and legacy SPI device configurations.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, configurable speed grade, and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
