SmartDV’s xSPI Verification IP is a comprehensive solution for verifying the JEDEC eXpanded Serial Peripheral Interface for Non-Volatile Memory Devices, the high-throughput, low-signal-count serial interface standard delivering up to 400 MB/s raw data throughput with limited backward compatibility to legacy SPI, used across computing, automotive, IoT, embedded, and mobile systems. Fully compatible with JESD251 and JESD251-1 standards, it supports complete verification of xSPI Master and Slave components across 4-wire, 7-wire, 8-wire, 11-wire, and 12-wire interfaces, data width up to 8 bits, 24-bit and 32-bit addressing, and both SDR and DDR data rate options.
SmartDV’s xSPI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With single, dual, quad, and Octal bus width operation, configurable clock polarity and phase, flexible erase operation, comprehensive power management commands, built-in functional coverage, and a complete test suite, SmartDV’s xSPI VIP enables verification teams to thoroughly validate xSPI interface designs for automotive ECUs, embedded microcontrollers, IoT devices, mobile SoCs, and any application requiring high-throughput non-volatile memory access with reduced pin count.
