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Overview

SmartDV’s V-By-One Transmitter IP is a silicon-proven, fully featured V-by-One HS video interface solution purpose-built for SoC designs requiring reliable, high-speed display video transmission across flat panel display, automotive infotainment, industrial camera, and machine vision applications. Fully compliant with V-by-One HS v1.52, it delivers complete transmitter-side V-by-One HS functionality supporting 1, 2, 4, 8, 16, and 32 lane configurations at data rates from 600 Mbps to 4 Gbps per lane, with comprehensive support for all standard video formats, resolutions, and refresh rates up to 4K at 240Hz — providing a proven, production-ready display interface transmitter for the most demanding high-resolution display SoC designs.

Designed to address the full breadth of V-by-One HS transmitter integration requirements, the IP supports RGB 4:4:4, YCbCr 4:4:4, RGBW/Y 4:4:4:4, and YCbCr 4:2:2 color formats across 16 to 40 bits per pixel, multi-byte mode configurations of 3, 4, and 5 bytes, configurable input pixels per clock from 1 to 8, 8b/10b encoding, scrambling, and flexible output data widths of 20, 40, and 80-bit parallel interface. Its 3D flag support for color and control data mapping gives display SoC teams a production-tested, spec-complete V-by-One HS transmitter that handles the full range of modern high-resolution display configurations with maximum signal integrity and flexibility.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane architecture, dynamic lane and byte mode configuration, and clean host interface enable fast integration and confident design bring-up across a wide range of display process nodes and target applications.

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V-By-One Transmitter
Key Features
  • Full V-By-One HS Transmitter Functionality – Complete transmitter-side implementation per V-by-One HS v1.52 supporting 1, 2, 4, 8, 16, and 32 lane configurations at 600 Mbps to 4 Gbps per lane
  • Comprehensive Color Format Support – RGB 4:4:4 (18/24/30/36 bpp), YCbCr 4:4:4 (18/24/30/36 bpp), RGBW/Y 4:4:4:4 (32/40 bpp), and YCbCr 4:2:2 (16/20/24/32 bpp)
  • Full Resolution and Refresh Rate Support – HD (1280×720), Full HD (1920×1080), Cinema Full HD (2560×1080), and 4K (3840×2160) at refresh rates up to 480Hz for Full HD and 240Hz for 4K
  • Flexible Multi-Byte Mode – Dynamic support for 3, 4, and 5 byte modes with configurable input pixel per clock of 1, 2, 4, and 8 for flexible display timing integration
  • Advanced Signal Processing – 8b/10b encoding and scrambling per V-by-One HS specification for robust high-speed serial signal transmission
  • Flexible Output Data Width – 20-bit, 40-bit, and 80-bit parallel output data width options for flexible PHY interface integration
  • 3D Display Support – Color data and control data mapping allocation to 3D flag for stereoscopic 3D display applications
Compliance and Compatibility
  • Fully compliant with V-by-One HS v1.52 specification (THine Electronics); backward compatible with v1.4, v1.3, and v1.2
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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