SmartDV’s V-By-One Receiver IP is a silicon-proven, fully featured V-by-One HS video interface solution purpose-built for SoC designs requiring reliable, high-speed display video reception across flat panel display, automotive infotainment, industrial camera, and machine vision applications. Fully compliant with V-by-One HS v1.52, it delivers complete receiver-side V-by-One HS functionality supporting 1, 2, 4, 8, 16, and 32 lane configurations at data rates from 600 Mbps to 4 Gbps per lane, with comprehensive support for all standard video formats, resolutions, and refresh rates up to 4K at 240Hz — providing a proven, production-ready display interface receiver for the most demanding high-resolution display SoC designs.
Designed to address the full breadth of V-by-One HS receiver integration requirements, the IP supports RGB 4:4:4, YCbCr 4:4:4, RGBW/Y 4:4:4:4, and YCbCr 4:2:2 color formats across 16 to 40 bits per pixel, multi-byte mode configurations of 3, 4, and 5 bytes, configurable output pixels per clock from 1 to 8, lane deskew, 10b/8b decoding, descrambling, 20-bit parallel interface, and 3D flag support for color and control data mapping. Its comprehensive error detection and reporting capability gives display SoC teams a production-tested, spec-complete V-by-One HS receiver that handles the full range of modern high-resolution display configurations.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane architecture, dynamic lane and byte mode configuration, and clean host interface enable fast integration and confident design bring-up across a wide range of display process nodes and target applications.
