UHS-II VIP

Simulation

Key Features Compliance and Compatibility Request a Datasheet

Overview

SmartDV’s UHS-II Verification IP is a comprehensive solution for verifying the SD Association Ultra High Speed Phase II interface, the LVDS-based high-bandwidth bus extending the SD card ecosystem for high-definition content, professional photography, and video applications. Fully compliant with SD Specification UHS-II Addendum Version 2.00, Part E1 SDIO Specification Version 4.10, and SD Specification Physical Layer Versions 4.0 through 9.1, it supports complete verification of UHS-II Host and Device components across bi-directional receiver/transmitter pairs supporting full duplex and half duplex modes, PHY-LINK interface, point-to-point and ring connection topologies, and RCLK frequencies from 26 to 56 MHz.

SmartDV’s UHS-II VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With complete data transaction coverage for SD-TRAN and CM-TRAN, 8b10b encoding and decoding, serializer/deserializer (SERDES) support, comprehensive error injection across all protocol layers, built-in functional coverage, and a complete test suite, SmartDV’s UHS-II VIP enables verification teams to thoroughly validate UHS-II interface designs for professional cameras, drones, gaming handhelds, automotive infotainment, and any application requiring high-bandwidth removable SD storage beyond UHS-I speeds.

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Key Features

Full UHS-II Host and Device Support – Provides complete UHS-II Host and Device component verification across bi-directional receiver and transmitter pairs (2ch) supporting both full duplex and half duplex modes, PHY-LINK interface, point-to-point and ring connection topologies, and RCLK frequency coverage from 26 to 56 MHz.
Comprehensive Speed Mode Coverage – Supports Full Duplex mode at data rates from 39MB/sec to 156MB/sec in Version 1.02, enhanced to 624MB/s maximum in Version 2.00, Half Duplex with 2 Lanes mode at 78MB/sec to 312MB/sec across Range A and Range B, and additional lane configurations including Full Duplex with 2 Downstream/1 Upstream, 1 Downstream/2 Upstream, and 2 Downstream/2 Upstream Lanes modes, with high-speed interface support up to 312MB/s for Version 1.02 and 624MB/s for Version 2.00.
Data Transaction Coverage – Supports single byte, single block, multiple block finite and infinite transfers, and MMC stream transfer operations, with complete data transaction support for both SD-TRAN and CM-TRAN covering fixed and infinite transfer lengths.
Power and Mode Management – Supports fast mode and low power mode, hibernate mode, power saving mode, enumeration, clock phase adjustment, and low voltage 1.8V card support for comprehensive UHS-II power state and initialization verification.
Advanced Card Feature Coverage – Supports lock-unlock and erase operation card features, video class specification, flow control operations, function extension commands, test modes, card ownership protection, discard and full user area logical erase, cache operation, command queuing, and card maintenance background operations.
Physical Layer and Encoding Coverage – Supports 8b10b encoding and decoding, serializer and deserializer (SERDES) implementation, and bus-accurate timing for complete UHS-II physical layer signal integrity verification.
Comprehensive Error Injection and Detection – Detects and reports all defined UHS-II error types including out of range errors, address misalign errors, CRC errors, switch errors, illegal command errors, block length errors, lock-unlock failed errors, erase sequence errors, stuff bit errors, invalid voltage errors, reserved bit errors, WP violation errors, CSD/CID overwrite errors, disparity error insertion, invalid and missing K character errors, link layer error injection, initialization error injection, illegal header errors, device specific errors, retry expiry errors, frame errors, and scrambler errors.
Complete Verification Infrastructure – Provides a full test suite covering all SDIO 4.10, SD Physical Layer, and UHS-II Addendum 2.00 specification features, built-in functional coverage analysis, status counters for bus events, and complete notification of all protocol and timing violations.

Compliance and Compatibility

Fully compliant with SD Specification UHS-II Addendum Version 2.00; backward compatible with Version 1.02
Compliant with Part E1 SDIO Specification Version 4.10
Compliant with SD Specification Physical Layer Versions 4.0 through 9.1
Supports speeds up to 624MB/s with Full Duplex and Half Duplex 2-Lane modes
Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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