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Overview

SmartDV’s SATA Host IP is a silicon-proven, fully featured Serial ATA host controller solution purpose-built for SoC designs requiring reliable, high-performance connectivity to SATA storage devices across embedded, industrial, automotive, and consumer electronics applications. Fully compliant with SATA Revision 3.5 and backward compatible with all prior SATA revisions from 2.5 onwards, it delivers complete host-side SATA functionality at 1.5, 3.0, and 6.0 Gbps with hardware support for Native Command Queuing, 48-bit addressing, First Party DMA, Port Multiplier, and Port Selector, providing a proven, production-ready SATA host controller for the most demanding storage subsystem designs.

Designed for the practical integration requirements of modern storage-intensive SoC designs, the IP implements the complete link layer state machine, 8b/10b encoding and decoding, CRC generation and checking, auto insertion of HOLD primitives, selectable data scrambling, link layer power modes, and CONT primitive support for EMI reduction. Its DMA and PIO command support, shadow register block, and serial ATA status and control registers give SoC teams a production-tested, spec-complete SATA host controller that connects seamlessly to the widest range of commercial SATA HDD, SSD, and optical storage devices.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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SATA Host
Benefits
  • Full SATA Host Controller Functionality – Complete host-side implementation per SATA Revision 3.5 supporting 1.5 Gbps, 3.0 Gbps, and 6.0 Gbps data transfer rates
  • Native Command Queuing (NCQ) – Hardware NCQ support with First Party DMA (FPDMA) for optimized storage throughput and reduced host processor overhead
  • Complete Link Layer – Full link layer state machine with 8b/10b encoding/decoding, CRC generation and checking, auto insertion of HOLD primitives, and selectable data scrambling
  • 48-Bit Address Support – Hardware 48-bit address set support for storage devices exceeding 128 GB capacity
  • Port Multiplier and Port Selector – Hardware Port Multiplier and Port Selector support for flexible multi-device storage topology integration
  • EMI Reduction – CONT primitive support for primitive suppression to reduce electromagnetic interference in sensitive embedded and industrial environments
  • Link Layer Power Management – Full link layer power mode support for power-efficient storage host operation
  • DMA and PIO Commands – Complete DMA and PIO command support with shadow register block and serial ATA status and control registers
Compliance and Compatibility
  • Fully compliant with SATA Revision 3.5; backward compatible with SATA Revision 3.4, 3.3, 3.2, 3.1, 3.0, 2.6, and 2.5
  • Supports 1.5 Gbps, 3.0 Gbps, and 6.0 Gbps SATA data transfer rates
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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