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Overview

SmartDV’s SAS Verification IP is a comprehensive solution for verifying the Serial Attached SCSI point-to-point serial storage interconnect, the enterprise storage industry standard for connecting hard disk drives, solid-state drives, tape drives, and storage arrays to host bus adapters and RAID controllers. Fully compliant with SAS-4 (INCITS 534-2019) and SAS Protocol Layer SPL-5 (INCITS 554-2023), and backward compatible with SAS-3, SAS-2, and SAS-1, it supports complete verification of SAS Initiator and Target components across trained speeds from 1.5 Gbps through 22.5 Gbps, SSP, STP, and SMP protocol layers, expander device models, retimer device models, narrow and wide port configurations, SCSI, ATA, and management frame transactions, zone permission configuration, and the complete SAS physical, link, and transport layer state machine suite.

SmartDV’s SAS VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive OOB sequence generation and checking, 8b/10b and 128b/130b encoding with FEC, SNW-3 phy capabilities, spread spectrum clocking, BMC encoding, interleaved SPL packet mode, complete SCSI command set, HDD model with LBA configuration, zone permission management, single and multi-bit error injection, built-in functional coverage, and a complete test suite, SmartDV’s SAS VIP enables verification teams to thoroughly validate SAS interface designs for enterprise HBAs, RAID controllers, SAS expanders, storage arrays, and server storage subsystem applications.

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SAS VIP
Key Features
  • Full SAS Initiator and Target Support – Provides complete SAS Initiator and Target component verification with Host, Device, and Monitor components, supporting narrow ports and wide ports, expander device model functionality, retimer device model, discover process, phy power conditions, successful low phy power condition handshake sequences, SATA spin-up and port selectors, management application client model for APTA, and configurable phy layer timers.
  • Physical Layer Coverage – Supports trained operation at 1.5, 3, 6, 12, and 22.5 Gbps and untrained operation at 1.5, 3, and 6 Gbps, complete 8b/10b encode and decode functions with error injection, 128b/130b encoding with Forward Error Correction for SAS-4 operation, interleaved SPL packet mode encoding and decoding, OOB sequence generation and checking, configurable OOB signals, SAS Dword mode and Packet mode, BMC encoding, SNW-3 phy capabilities bits, spread spectrum clocking modulation, physical link rate tolerance management, and Train_Tx-SNW and Train_Rx-SNW for both Dword and Packet modes.
  • Link Layer Coverage – Supports STP, SSP, and SMP link layer connections, link layer rate matching for both SAS Dword and Packet modes, SAS speed negotiation sequence, link reset sequence, address frames, reset sequences, phy reset sequences, SAS domain changes, complete power control, identification and hard reset link layer state machines, complete SAS logical phys, expander logical phys, SSP, STP, and SMP link layer state machines, configurable port control mode page, and STP flow control.
  • Transport and Application Layer Coverage – Supports SSP, STP, and SMP frame fields and frame field errors, SCSI, ATA, and management frame transactions, standard SCSI, SMP, and STP commands, parameter storage with mode pages and log pages, LBA with HDD size configuration, backdoor HDD access APIs, programmable auto-activate support, configurable FIS latencies, FIFO depths and FIS size, and SATA features including software settings preservation and hardware feature control.
  • Expander and Zone ManagementSupports expander device model features and expander device handling of connections, zone permission configuration, expander connection handling, STP flow control, and management frame transactions for complete SAS topology verification.
  • Advanced HDD Feature SupportSupports non-512 byte sector size, HDD activity activation, automatic partial to slumber transitions, DHU specific operation, Rebuild Assist, Hybrid Information Feature, and Device Signature returns Feature.
  • Comprehensive Error Injection and Protocol Checking – Supports single and multi-bit error injection, 8b/10b encoding and decoding error injection, randomized and directed CRC error injection and checking, complete disparity checking, complete K-code and D-code validity and alignment checking, scrambling enable and disable on the fly, selectable primitive CONT and fill substitution processing, user-defined primitive and frame transmission, and configurable transmit and receive FIFO latencies.
  • Complete Verification Infrastructure – Provides a full test suite covering all SAS-4 and SPL-5 specification features, built-in functional coverage analysis, callbacks in Host, Device, and Monitor for user-defined data processing, and complete notification of all protocol and timing violations.
Compliance and Compatibility
  • Fully compliant with SAS-4 (INCITS 534-2019) at 22.5 Gbps; backward compatible with SAS-3 (12 Gbps), SAS-2 (6 Gbps), and SAS-1 (3 Gbps and 1.5 Gbps)
  • Compliant with SAS Protocol Layer SPL-5 (INCITS 554-2023)
  • Supports SSP, STP, and SMP protocol layers with expander device model
  • Supports 8b/10b encoding (SAS-1/2/3) and 128b/130b with FEC (SAS-4)
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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