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Overview

SmartDV’s SAS Initiator IP is a silicon-proven, fully featured Serial Attached SCSI solution purpose-built for SoC designs requiring high-performance, reliable storage connectivity across enterprise, data center, and high-performance embedded applications. Fully compliant with SPL-5 (INCITS 554-2023) and SAS-4.1 (INCITS 567-2023), it delivers complete initiator-side SAS functionality supporting data transfer rates from 1.5 Gbps through 22.5 Gbps across SSP, SMP, and STP protocols, with full SATA tunneling support at 1.5, 3, and 6 Gbps — providing a proven, production-ready storage interface foundation for the most demanding HBA and storage controller designs.

Designed to address the full breadth of SAS initiator requirements, the IP implements the complete PHY, link, and transport layer stack including OOB sequence generation, SNW-3 capability negotiation, spread spectrum clocking, forward error correction, interleaved SPL packet mode, and SAS Dword and Packet mode operation. Its support for narrow and wide ports, BMC encoding, 8b/10b encode/decode, complete K and D code validity checking, and DMA and PIO commands gives storage SoC teams a production-tested, spec-complete SAS initiator that handles the full range of SAS and SATA storage device types with maximum protocol compliance.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its native 32-bit PHY interface, configurable parallel interface widths, and clean host interface enable fast integration and confident design bring-up across a wide range of enterprise storage process nodes and target applications.

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SAS Initiator
Benefits
  • Full SAS Initiator Functionality – Complete initiator-side implementation per SPL-5 and SAS-4.1 supporting SAS data rates of 1.5, 3, 6, 12, and 22.5 Gbps and SATA data rates of 1.5, 3, and 6 Gbps
  • Complete Protocol Stack – SSP, SMP, and STP transport protocols with full link layer connections, flow control, and address frame support for comprehensive SAS and SATA device coverage
  • Advanced PHY Layer – OOB sequence generation and checking, SNW-3 PHY capability bits, spread spectrum clocking, BMC encoding, complete 8b/10b encode/decode, and K/D code validity checking
  • SAS Dword and Packet Mode – Both SAS Dword mode and Packet mode operation with forward error correction encoding/decoding and interleaved SPL packet mode encoding/decoding
  • Narrow and Wide Port Support – Both narrow and wide port configurations with physical link rate tolerance management and all PHY power conditions and management
  • Complete PHY State Machines – Full resynchronization PHY layer state machines, Train Tx/Rx SNW for both Dword and Packet modes, and complete overall control and PHY control state machines
  • SATA Feature Support – Device signature returns feature, shadow register block, serial ATA status and control registers, and DMA and PIO command support for complete SATA tunneling
  • Flexible PHY Interface – Native 32-bit PHY interface with 10, 20, and 40-bit parallel interface support and configurable primitive CONT and fill substitution processing
Compliance and Compatibility
  • Fully compliant with SPL-5 (INCITS 554-2023); backward compatible with SPL 1.0 through SPL 4.0
  • Fully compliant with SAS-4.1 (INCITS 567-2023); backward compatible with SAS-4, SAS-3, SAS-2, and SAS-1
  • Supports SATA 1.5, 3, and 6 Gbps via STP tunneling
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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