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Overview

SmartDV’s SATA Verification IP is a comprehensive solution for verifying the Serial ATA storage interface, the industry-standard point-to-point serial bus connecting host controllers to hard disk drives, solid-state drives, and optical drives in consumer, enterprise, and embedded storage applications. Fully compliant with SATA Revision 3.5 (July 2020) and backward compatible with Revisions 3.4, 3.3, 3.2, 3.1, 3.0, 2.6, and 2.5, it supports complete verification of SATA Host and Device BFM components across 1.5, 3, and 6 Gbps speeds, all FIS types, all ATA command sets including NCQ, Port Multiplier discovery and enumeration, link layer power modes, Zone Aligned Commands (ZAC), FPDMA Zone Management, ACS-4 commands, asynchronous notification, asynchronous signal recovery, and enclosure management services.

SmartDV’s SATA VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With comprehensive OOB sequence generation and checking, 8b/10b encoding with error injection, digital SERDES model, PIPE interface support, configurable FIFO latencies and depths, scrambling control, single and multi-bit error injection, LBA and HDD model with backdoor access, built-in functional coverage, and a complete test suite, SmartDV’s SATA VIP enables verification teams to thoroughly validate SATA interface designs for storage controllers, HBAs, SATA bridge chips, system-on-chip storage subsystems, and enterprise storage applications.

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SATA VIP
Key Features
  • Full SATA Host and Device BFM Support – Provides complete SATA Host and Device BFM verification with selectable Host or Device configuration, digital SERDES model, PIPE interface support, 8, 16, 32, and 64-bit SERDES interface widths, 1-bit, 8-bit, 10-bit, 20-bit, 32-bit, 40-bit, and 64-bit interface configurations, complete link layer state machine, callbacks for state transitions, primitive and FIS reception and transmission, OOB transmission and reception, and speed change handling.
  • Physical Layer Coverage – Supports 1.5, 3, and 6 Gbps speeds, OOB sequence generation and checking, configurable OOB signals and speed of operation, speed switching and negotiation, asynchronous signal recovery, spread spectrum clocking, complete 8b/10b encode and decode functions, disparity checking, K-code and D-code validity and alignment checking, configurable phy layer timers, and selectable data scrambling with on-the-fly enable and disable.
  • Link Layer CoverageSupports selectable primitive CONT and fill substitution processing, link layer power modes including Partial and Slumber with automatic Partial to Slumber transitions, SYNC injection during FIS transfer, programmable enable and disable of DMAT, CONT, and HOLD primitives with configurable duration, configurable transmit and receive FIFO latencies, user-defined primitive transmission, and user-defined primitives and frame transmission.
  • Transport and Application Layer Coverage – Supports all standard ATA command sets including NCQ, intermixing of non-native queued commands with native queued commands, FPDMA Zone Management commands, queued version of ACS-4 Zero EXT command, Receive FPDMA Queued for ZAC support, Data Set Management aligned with ACS-4, Data Set Management XL command, ZAC Management Logs for NCQ non-data and Send/Receive FPDMA commands, Set Features support, Device Configuration Overlay, Software Settings Preservation, and Hardware Feature Control.
  • Port Multiplier and Advanced Features – Supports Port Multiplier discovery and enumeration, asynchronous notification, staggered spin-up, non-512 byte sector size, enclosure management and services, HDD activity activation, DHU specific operation, Rebuild Assist, Hybrid Information Feature, Device Signature returns Feature, optional DC-IDLE pin, SATA logs, and out of band management control structures.
  • HDD Model and Error InjectionSupports LBA with HDD size configuration, APIs providing backdoor HDD access, programmable auto-activate support, configurable FIS latencies and FIFO depths and FIS size, single and multi-bit error injection, 8b/10b encoding and decoding error injection, randomized and directed CRC error injection and checking, and bit error controls.
  • Complete Verification Infrastructure – Provides a full test suite covering all SATA Revision 3.5 specification features, built-in functional coverage analysis, callbacks in Host, Device, and Monitor for user-defined data processing, and complete notification of all protocol and timing violations.
Compliance and Compatibility
  • Fully compliant with SATA Revision 3.5 (July 2020); backward compatible with Revisions 3.4, 3.3, 3.2, 3.1, 3.0, 2.6, and 2.5
  • Supports 1.5 Gbps (Gen 1), 3 Gbps (Gen 2), and 6 Gbps (Gen 3) speeds
  • Supports NCQ, ZAC, FPDMA Zone Management, and ACS-4 command sets
  • Supports Port Multiplier discovery and enumeration
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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