SmartDV’s SATA Synthesizable Transactor is a fully featured Serial ATA bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable SATA Host and Device behavior during pre-silicon validation of HDD, SSD, and embedded storage SoC designs. Fully compliant with SATA Revision 3.5 and backward compatible with all prior SATA revisions from 2.5 onwards, it delivers complete Host and Device functionality at 1.5, 3.0, and 6.0 Gbps, giving validation teams a drop-in synthesizable SATA transactor ready for rapid integration into emulation and prototyping flows.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports complete link layer state machine modeling, 8b/10b encoding and decoding, CRC generation and checking, auto insertion of HOLD primitives, Native Command Queuing with maximum queue depth of 32, First Party DMA, Port Multiplier, Port Selector, selectable data scrambling, CONT primitive for EMI reduction, link layer power modes, DMA and PIO commands, shadow register block, and device signature returns, enabling validation teams to exercise corner-case SATA behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deployable on any hardware emulation or FPGA prototyping platform. Its comprehensive error injection capabilities, testbench notification of significant events, warnings, timing, and protocol violations enable rapid deployment for early software bring-up and storage system-level validation regardless of the underlying emulation platform.
