SmartDV’s MIPI TWP Formatter IP is a silicon-proven, fully featured Trace Wrapper Protocol encoder purpose-built for SoC designs requiring efficient, standards-compliant merging of multiple on-chip trace streams into a single unified output for storage, export, or debug tool consumption. Fully compliant with MIPI TWP v1.1, it implements the complete TWP wrapping architecture, combining trace from up to 111 source streams, including STP, processor trace, and custom trace sources, into a single 128-bit framed output with approximately 6% bandwidth overhead for a single continuous source.
Designed as the central trace aggregation block within the Debug and Test System (DTS) side of a complete MIPI debug and trace infrastructure, the IP generates all three TWP layers: T3 mandatory 16-byte Data frames, T2 Alignment Synchronization Frame Sync Packets, and T1 Flow Control Padding Packets, alongside special source IDs for NULL padding (0x00), trigger (0x7D), marker (0x7C), and flush marker (0x7B, added in v1.1). Its ARM CoreSight Trace Formatter compatibility, Gigabit Trace support for export over functional networks such as USB, and trigger indication to the debug and test controller give SoC teams a production-tested, ecosystem-compatible trace formatter that integrates seamlessly with PTI, HTI, and GbT network adaptors.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean on-chip interface enable fast integration and confident design bring-up across a wide range of process nodes and debug infrastructure applications.
