SmartDV’s MIPI TWP Decoder IP is a silicon-proven, fully featured Trace Wrapper Protocol decoder purpose-built for debug infrastructure requiring accurate, standards-compliant recovery of individual trace streams from a merged TWP-formatted input. Fully compliant with MIPI TWP v1.1, it implements the complete TWP de-wrapping architecture, parsing a single 128-bit framed input and reconstructing up to 111 independent source trace streams, including STP, processor trace, and custom trace sources, for delivery to downstream storage, export, or debug tool consumption.
Designed as the central trace de-aggregation block within the Debug and Trace Controller (DTC) side of a complete MIPI debug and trace infrastructure, the IP parses all three TWP layers: T3 mandatory 16-byte Data frames, T2 Alignment Synchronization Frame Sync Packets, and T1 Flow Control Padding Packets, correctly identifying special source IDs for NULL padding (0x00), trigger (0x7D), marker (0x7C), and flush marker (0x7B, added in v1.1) as it reconstructs each source stream. Its ability to recover decode alignment from any position in the stream via Frame Synchronization Packets, even after data loss or a lost stream start, makes it a robust, ecosystem-compatible complement to PTI, HTI, and GbT network adaptors, and a natural pairing with ARM CoreSight-based debug tooling.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean on-chip interface enable fast integration and confident design bring-up across a wide range of process nodes and debug infrastructure applications.
