SmartDV’s MIPI TWP Verification IP is a comprehensive solution for verifying the MIPI Trace Wrapper Protocol, a byte-stream merging protocol that combines multiple independent source trace streams into a single unified trace stream for export via high-speed trace interfaces such as MIPI HTI and MIPI PTI. Based on ARM CoreSight Trace Formatter Protocol and fully compliant with MIPI TWP v1.1, it supports complete verification of TWP Debug and Test System and Debug and Trace Controller components across the TWP interface between DTS and DTC, up to 111 source trace streams, all three defined layer types, synchronization point generation, trigger event positioning, output padding, and transport-agnostic bit stream export across any transport supporting bit stream data.
SmartDV’s MIPI TWP VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With low additional bandwidth overhead, efficient memory storage for later retrieval, decode recovery from any stream position via synchronization points, complete layer coverage for Flow Control, Alignment Synchronization, and Data, built-in functional coverage, and a complete test suite, SmartDV’s MIPI TWP VIP enables verification teams to thoroughly validate trace wrapper protocol interface designs for mobile SoCs, automotive ECUs, IoT devices, and any embedded system requiring multi-source trace stream merging and standardized export.
