SmartDV’s MIPI TWP Synthesizable Transactor is a fully featured Trace Wrapper Protocol bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable TWP trace wrapping and de-wrapping behavior during pre-silicon validation of mobile, automotive, and embedded SoC debug and trace infrastructure designs. Fully compliant with MIPI TWP v1.1, it delivers complete TWP encoder and decoder functionality supporting up to 111 source trace streams combined into a single unified stream, giving validation teams a drop-in synthesizable TWP transactor ready for rapid integration into emulation and prototyping flows alongside STP, HTI, and PTI trace infrastructure components.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports all three TWP layers — T1 Flow Control via Padding Packets, T2 Alignment Synchronization via Frame Synchronization Packets, and T3 Data via TWP Frames — alongside error handling and flushing mechanisms, all Debug CCCs and opcodes, and string transmission for SoC verification, enabling validation teams to exercise corner-case TWP trace behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its on-the-fly protocol and data checking and testbench notification of transactions, warnings, and protocol violations enable rapid deployment for early software bring-up and trace infrastructure validation regardless of the underlying emulation platform.
