SmartDV’s MIPI STP Verification IP is a comprehensive solution for verifying the MIPI System Trace Protocol, a generic base wrapper protocol that merges trace streams from multiple independent trace sources within an SoC into a unified trace stream for system-level debug and analysis. Fully compliant with MIPI STP v2.4 (February 2024) and backward compatible with v2.3, v2.2, and v2.0, it supports complete verification of STP master and slave components across STP, ATB, and TPIU interfaces, up to 65,536 independent data Masters with up to 65,536 channels per Master, all defined packet types including basic trace data, timestamped data in all four timestamp formats, flag packets, trigger packets, synchronization packets, platform description packets, channel error messages, and user-defined data packets.
SmartDV’s MIPI STP VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive timestamp format coverage, cross-synchronization event support, stream synchronization on bit and message boundaries, comprehensive error injection and detection, constraints randomization, built-in functional coverage, and a complete test suite, SmartDV’s MIPI STP VIP enables verification teams to thoroughly validate system trace protocol interface designs for mobile SoCs, automotive ECUs, IoT devices, and any embedded system requiring standardized multi-source trace stream merging and export.