SmartDV’s MIPI STP (System Trace Protocol) Verification IP is designed to verify trace and debug data transport in complex SoC architectures. Fully compliant with the MIPI STP specification, this VIP enables accurate verification of real-time trace streams carried over parallel or serial interfaces, ensuring visibility into embedded system behavior during development and validation.
The VIP supports major verification languages, including SystemVerilog and Verilog, and integrates seamlessly with methodologies such as UVM, OVM, and VMM. It is simulator-independent and compatible with all leading EDA vendors’ simulators, providing flexibility for a wide range of simulation environments.
With configurable source and sink agents, built-in checkers, support for timestamping, data alignment, and multi-channel trace, SmartDV’s MIPI STP VIP helps verification teams validate system-level trace functionality in embedded, automotive, and mobile SoCs.