SmartDV’s MIPI STP Major Source IP is a silicon-proven, fully featured System Trace Protocol trace generation solution purpose-built for SoC designs requiring standards-compliant, on-chip aggregation and encoding of software instrumentation and hardware event trace data. Fully compliant with MIPI STP v2.4, it implements a complete Major Source STP encoder, generating well-formed STP nibble streams tagged with Major Source and Channel identifiers across a 65,536 x 65,536 source/channel address space, for seamless integration into a complete MIPI debug and trace infrastructure.
Designed to address the trace generation requirements of modern multi-core, multi-subsystem SoC designs, the IP supports data packets of 4, 8, 16, 32, and 64-bit widths with marked and timestamped variants, multiple timestamp formats including Gray code, natural binary, delta, and legacy STPv1, and a comprehensive packet type set including FLAG, TRIG, XSYNC, PDID, USER, and ASYNC synchronization packets. Its byte-packed output stream is fully compatible with TWP wrapping for direct merging with other trace sources or export via PTI, HTI, or trace buffer, giving SoC teams a production-tested, spec-complete trace source implementation that integrates cleanly into any MIPI-based debug infrastructure.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean on-chip interface enable fast integration and confident design bring-up across a wide range of process nodes and target SoC applications.
