SmartDV’s MIPI STP Synthesizable Transactor is a fully featured System Trace Protocol bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable STP trace source and decoder behavior during pre-silicon validation of mobile, automotive, and embedded SoC debug and trace infrastructure designs. Fully compliant with MIPI STP v2.4 and backward compatible with v2.2, it delivers complete STP trace generation and decoding functionality supporting up to 65,536 independent trace sources (Major Sources) with full channel addressing, giving validation teams a drop-in synthesizable STP transactor ready for rapid integration into emulation and prototyping flows.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports trace data merging from up to 65,536 independent Major Sources, user-defined data packets, optional data integrity protection of the trace stream, bit and message boundary synchronization facilities, and string transmission for SoC verification, enabling validation teams to exercise corner-case STP trace behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its complete test suite covering every feature of the MIPI STP specification, on-the-fly protocol and data checking, and testbench notification of transactions, warnings, and protocol violations enable rapid deployment for early software bring-up and trace infrastructure validation regardless of the underlying emulation platform.
