SmartDV’s MIPI STP Decoder IP is a silicon-proven, fully featured System Trace Protocol decode solution purpose-built for debug and test system designs requiring reliable, standards-compliant reconstruction of STP trace streams captured from a target SoC. Fully compliant with MIPI STP v2.4 including Errata 01 corrections for error packet encodings, it implements a complete STP nibble stream decoder, consuming incoming STP streams after TWP de-wrapping where applicable, and reconstructing the original instrumentation messages with full Major Source and Channel attribution, timestamp recovery, and payload extraction across the complete 65,536 x 65,536 source/channel address space.
Designed to address the practical decode challenges of real-world trace capture environments, the IP supports all STP timestamp formats including Gray code, natural binary, delta, and legacy STPv1, and decodes the full STP opcode set including MERR, CERR, GERR error packets, TRIG, FLAG, VERSION, TIME, PDID, and USER packets. Its ASYNC-based receiver synchronization, resilient resynchronization after data loss, and data integrity protection verification give debug tool and DTS teams a production-tested, spec-complete decoder that delivers accurate, complete trace interpretation from any MIPI STP v2.4 compliant trace source.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean DTS-side interface enable fast integration and confident design bring-up across a wide range of process nodes and debug system applications.
