SmartDV’s MIPI SPP Verification IP is a comprehensive solution for verifying the MIPI SneakPeek Protocol, the standardized debug communications protocol connecting Debug and Test Systems with Target Systems through address-mapped read and write transactions that abstract the underlying debug transport interface. Fully compliant with MIPI SPP v2.2 (April 2026) and backward compatible with v2.1, v2.0, and v1.0, it supports complete verification of SPP Debug and Test System and Target System components across independent full-duplex communication, Full SPP and Tiny SPP packet types, all defined opcodes, dynamic SPTB sizing, up to 32 access spaces with 32-bit configuration register addressing, 64-bit system address width, JTAG Access Space, Secure Communication Manager Access Space, and comprehensive error injection and detection across all defined SPP error types.
SmartDV’s MIPI SPP VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With normal and error response generation, complete configuration register and access space verification, JTAG packetized messaging, secure debug communication support, built-in functional coverage, and a complete test suite, SmartDV’s MIPI SPP VIP enables verification teams to thoroughly validate SneakPeek Protocol debug interface designs for mobile SoCs, IoT devices, automotive ECUs, and any embedded system requiring standardized transport-agnostic debug connectivity.
