SmartDV’s MIPI SPP Synthesizable Transactor is a fully featured SneakPeek Protocol debug bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable SPP Debug and Test System (DTS) and Target System (TS) behavior during pre-silicon validation of mobile, automotive, and embedded SoC debug infrastructure designs. Fully compliant with MIPI SPP v2.2 and backward compatible with v2.0, it delivers complete SPP debug functionality including all Debug CCCs, opcodes, error handling methods, and JTAG integration, giving validation teams a drop-in synthesizable SPP transactor ready for rapid integration into emulation and prototyping flows.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports both FullSPP header structure for high-speed mode operation and TinySPP (4-byte header derivative) for low-bandwidth deployments, all Debug CCCs and opcodes, action and event indications, JTAG-related opcodes within SneakPeek packets, and string transmission for SoC verification, enabling validation teams to exercise corner-case SPP debug behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its complete test suite covering every feature of the MIPI SPP specification, on-the-fly protocol and data checking, and testbench notification of transactions, warnings, and protocol violations enable rapid deployment for early software bring-up and debug infrastructure validation regardless of the underlying emulation platform.
