SmartDV’s MIPI SPP DTS IP is a silicon-proven, fully featured SneakPeek Protocol Debug and Test System solution purpose-built for SoC designs requiring standards-compliant, host-side debug command engine functionality. Fully compliant with MIPI SPP v2.2, it implements the complete DTS-side SneakPeek Protocol engine, originating Command Packets, packing them into SneakPeek Transfer Blocks (SPTBs) for network-efficient transport, and tracking and interpreting returned Response Packets — all over a functional network behind an SPP Network Adaptor operating on in-order, lossless, full-duplex assumptions.
Designed to give debug tool and DTS teams a production-tested, spec-complete host-side implementation, the IP manages complete Debug Management Agent and SneakPeek session state machines alongside full support for Memory, JTAG, and Fabric Agent types. Its SPTB packing of multiple Command Packets for network efficiency, TinySPP address tracking, reaction logic for error conditions, and Secure Communication Manager Access Space via SPDM-based flows gives SoC and debug tool teams a future-ready DTS implementation capable of establishing secure debug sessions with production target systems in field environments.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, network-adaptor-friendly design, and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and debug system applications.
